Are you confident in explaining how a chip is built from RTL to GDSII?
Most students aren’t.
This 30-day intensive VLSI internship is designed to bridge that gap with practical, industry-oriented learning.

💡 What you’ll learn:

• RTL Design & Verification

• Synthesis & Static Timing Analysis (STA)

• Floorplanning, Placement, CTS, Routing

• Complete RTL → GDSII Flow

• 📅 Start Date: May 1, 2026

• ⏳ Duration: 30 Days

• 💻 Mode: Online

• 💰 Fee: ₹2400

• 📱UPI ID:

• ⚠️ Limited seats to ensure quality learning.